TCP/IP Protocol Stack

Overview

The TCP/UDP/IP Protocol Stack is a hardware networking core that implements the Ethernet communication protocols required for reliable data exchange over IP networks. It enables FPGA-based systems to transmit and receive Ethernet frames using industry-standard protocols including ARP, IPv4, TCP, and UDP while providing deterministic, low-latency communication.

Implemented entirely in hardware, the protocol stack offloads network processing from software, significantly reducing CPU overhead while improving throughput and lowering latency. The core provides packet parsing, checksum generation and validation, ARP address resolution, IP routing, and TCP/UDP communication. It interfaces to a Gigabit Ethernet MAC through AXI4-Stream interfaces and with user logic through dedicated TCP, UDP, and streaming interfaces, making it suitable for high-performance real-time FPGA applications.

INTERFACE BLOCK DIAGRAM

A simplified interface block diagram showing the core's external interfaces and integration points.

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Architecture

• • High-Speed Payload Buffering — Buffers TCP transmit payloads to absorb application-to-link rate differences and support retransmission without application resends.
• • Per-Engine Header Generation and Checksum Calculation — Each transmit engine assembles complete Ethernet/IP/protocol headers, calculates checksums in hardware, and outputs fully formed frames.
• • Hardware Checksum Verification — Verifies received IPv4, TCP, and UDP checksums in hardware.
• • Address Cache — Stores dynamic IP-to-MAC mappings to eliminate repeated address-resolution requests.
• • Address Resolution (ARP) — Resolves IPv4 addresses to MAC addresses, processes replies, updates the cache, responds to requests for the local IP, and requests unresolved destinations.
• • ICMP — Processes ICMP packets and automatically detects and generates Echo Request/Reply messages (hardware Ping).
• • IGMP (Optional) — Supports IPv4 multicast by processing membership queries and generating membership reports.
• • Packet Filtering — Routes incoming packets by destination IP and TCP/UDP port to the correct internal interface; it is not an ACL-style forward/drop/mirror/redirect engine.
• • Transmit Arbiter — Schedules shared Ethernet MAC transmitter access across protocol engines, allowing one packet at a time with deterministic scheduling.
• • VLAN (Optional) — Provides single-VLAN 802.1Q access-port operation. Transmit frames use the configured VLAN ID and priority. Receive tags are stripped, while mismatched or untagged frames are dropped. Supports one VLAN per instance without multi-VLAN trunking.

MICRO-ARCHITECTURE BLOCK DIAGRAM

A detailed micro-architecture view showing the receive and transmit paths, protocol engines, TCP/UDP datapaths, buffering, and user-facing interfaces.

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Core Networking Features

• • 1/2.5 Gigabit Ethernet TCP/UDP/IP hardware protocol stack
• • Fully hardware-based protocol processing with no embedded CPU required
• • Low-latency, deterministic packet processing
• • High-throughput architecture optimized for FPGA implementation
• • Configurable number of concurrent TCP server/client sessions (resource dependent)
• • Automatic TCP connection establishment and termination
• • User-controlled TCP connection reset
• • Hardware TCP retransmission for reliable communication
• • Internal TCP transmit and receive buffering using FPGA BRAM/inferred RAM
• • AXI4-Stream interfaces for TCP, UDP, and Ethernet MAC
• • Automatic Ethernet, IPv4, TCP, and UDP header generation
• • Hardware checksum generation and validation for IPv4, TCP, and UDP
• • Automatic IP Identification (IP ID) generation
• • Shared packet parser supporting Ethernet, IPv4, TCP, UDP, ARP, and ICMP; per-engine frame assembly on transmit
• • Hardware transmission arbiter for sharing a single Ethernet MAC across multiple protocols
• • AXI4-Lite register interface for configuration and status

Advance Networking Feature

• • High-speed payload buffering
• • Hardware packet scheduler
• • IEEE 802.1Q VLAN tag insertion (transmit) and strip + isolation (receive) (optional)
• • Destination IP/port-based packet filtering (optional)

Deliverables

• • Synthesizable RTL source code
• • Complete simulation testbench
• • Example design
• • Integration guide
• • User documentation
• • Configuration examples

Support

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